The present invention relates to a high frequency differential amplifier.
1. Background to the Invention
Existing prior art low voltage differential stage receiver input output cells that condition, that is, which square up, low voltage differential high frequency signals, such as, for example, 622 MHz, are presently required to provide some form of hysteresis to prevent inadvertent output switching caused by either (a) a momentary high impedance state of the input signals, that is, floating inputs, or (b) packaging of effects such as ringing and signal overlap. The gain required for signal squaring at 622 MHz is substantial when implemented using a 0.18 micron CMOS process. It will be appreciated that the provision of the required hysteresis requires a corresponding increase in gain margin. Since, under worst-case conditions, the 622 MHz output is only just realisable using conventional circuit techniques, the minimum hysteresis value is at best only present under typical to worst-case conditions, if at all.
It is an object of the present invention at least to mitigate the above problems of the prior art.
2. Summary of the Invention
Accordingly, an embodiment of the present invention provides an amplifier comprising an input stage having at least one signal input terminal and a biasing arrangement arranged to bias the at least one signal input terminal, an output stage comprising a pair of FET transistors arranged such that the gates thereof are biased using a common mode gate bias voltage derived from a resistor divider formed between the output terminals of the pair of FET transistors.
Advantageously, embodiments of the present invention increase, and preferably maximise, the hysteresis above a level of 25 mV under all operating conditions.
It will be appreciated that such a hysteresis requires extra gain to give the required margin.
In an embodiment, if a 40 mV (xc2x120 mV) hysteresis is required, it will be appreciated that the effective minimum differential input signal amplitude value for the circuit without hysteresis changes from the xc2x1100 mV specified level to xc2x180 mV, ie the circuit gain needs to be appropriately increased. This embodiment achieves a 40 mV hysteresis.
Embodiments of the present invention allow the realisation of a high output impedance differential amplifier that is operable at high clocking speeds or that can process high frequency signals. This is in contrast to conventional output stages that use diode configured FETs that produce relatively low output impedances and which also suffer from the switching limitations imposed by the gates capacitances.